The Fetch–Decode–Execute Cycle

🎯 Syllabus & Goals 3 min

Cambridge 3.1 · Computer architecture Paper 1 · Computer Systems

By the end of this lesson you can:

1. Describe the fetch, decode and execute stages, naming the register and bus used at each step.
2. Trace the contents of the PC, MAR, MDR, CIR and ACC as a short program runs.
3. Define an instruction set, an opcode and an operand.

Textbook: Chapter 3, §3.1.2 Fetch–Decode–Execute cycle (pp. 79–80) and §3.1.4 Instruction set (p. 82)

Recap / Warm-Up 5 min

Last lesson you used the MAR and MDR to read and write one memory location. The fetch–decode–execute cycle uses exactly the same moves — billions of times a second.

Quick starter

To read a value from memory, which register receives the address first, and which one receives the value?

🧠 Key Concept 14 min

1 · One cycle per instruction

A program is a list of instructions stored in memory. The CPU runs it by repeating one cycle for every instruction. It fetches the instruction from memory, decodes it to work out what it means, then executes it.

2 · The cycle step by step

3 · Instruction sets: opcode + operand

Each machine instruction has two parts. The opcode tells the CPU what to do. The operand is the data to act on, or the address/register where that data is found.

A CPU only understands a limited number of opcodes. That complete list is its instruction set. Everything the computer runs must end up as instructions from this set, in binary. Examples of operations are LDA (load), ADD and JMP (jump to another address).

Worked Example 12 min

(a) Trace a three-instruction program

Memory holds a program at addresses 20–22 and data at 30–32. LDA 30 loads the value at address 30 into the ACC. ADD 31 adds the value at 31. STO 32 stores the ACC at address 32. The PC starts at 20.

1. Start from the PC: MAR ← 20.every fetch begins by copying the PC into the MAR.
2. The instruction comes back into the MDR, then the CIR: CIR = LDA 30.the MDR is only a waiting area; the CIR is where it is decoded.
3. The PC goes up by one: PC = 21.so the CPU already knows where the next instruction is.
4. Executing LDA 30 uses the MAR and MDR again, this time for data: ACC = 12.the same two registers carry instructions and data.
5. ADD 31 makes the ALU add 9: 12 + 9 = 21.the ACC holds the running result during ALU work.
6. STO 32 writes 21 into address 32. Memory[32] = 21.a write puts the data in the MDR and the address in the MAR.

(b) Decode binary instructions

A practice CPU uses 8-bit instructions: a 4-bit opcode then a 4-bit operand. Its opcodes are 0001 = LDA, 0010 = ADD, 0011 = STO, 0100 = JMP.

1. Split 0001 1110 into 0001 | 1110.the first four bits are always the opcode in this format.
2. Look up the opcode: 0001 = LDA.the CU decodes by matching the opcode against its instruction set.
3. Convert the operand: 1110 = 8 + 4 + 2 = 14.so this means "load the value at address 14".
4. 0100 0010 → opcode 0100 = JMP, operand 0010 = 2. The PC is set to 2.a jump changes the PC, so the next fetch comes from address 2.
5. How many opcodes can this CPU have? 4 bits → 2⁴ = 16.this limit is why an instruction set is a fixed, limited list.

(c) The cycle as a loop

The fetch stage written in Cambridge pseudocode (one statement per line):

Cambridge pseudocode

// Fetch, then decode and execute, until the program ends
DECLARE Memory : ARRAY[0:99] OF STRING
DECLARE PC, MAR : INTEGER
DECLARE MDR, CIR : STRING
DECLARE Finished : BOOLEAN
PC ← 20
Finished ← FALSE
REPEAT
  // fetch
  MAR ← PC
  MDR ← Memory[MAR]
  CIR ← MDR
  PC ← PC + 1
  // decode and execute
  IF CIR = "END"
    THEN
      Finished ← TRUE
    ELSE
      CALL DecodeAndExecute(CIR)
  ENDIF
UNTIL Finished = TRUE

The same program in Python (IDLE) — it runs the trace above

# A tiny fetch-decode-execute simulator
memory = {20: "LDA 30", 21: "ADD 31", 22: "STO 32", 23: "END",
          30: 12, 31: 9, 32: 0}
pc = 20
acc = 0
while True:
    mar = pc                   # fetch: address of next instruction
    mdr = memory[mar]          # instruction copied into the MDR
    cir = mdr                  # ...then into the CIR
    pc = pc + 1                # PC now points to the next instruction
    parts = cir.split()        # decode: opcode and operand
    opcode = parts[0]
    if opcode == "END":
        break
    operand = int(parts[1])
    if opcode == "LDA":
        acc = memory[operand]
    elif opcode == "ADD":
        acc = acc + memory[operand]
    elif opcode == "STO":
        memory[operand] = acc
    print(cir, "-> ACC =", acc, "| PC =", pc)
print("Address 32 now holds", memory[32])

Output

LDA 30 -> ACC = 12 | PC = 21
ADD 31 -> ACC = 21 | PC = 22
STO 32 -> ACC = 21 | PC = 23
Address 32 now holds 21

How the marks are earned on a "describe the fetch stage" question: PC holds the address (1) · copied to the MAR via the address bus (1) · instruction copied to the MDR via the data bus (1) · MDR copied to the CIR (1) · PC incremented (1).

Try It Yourself 12 min

📝 Exam Practice 10 min

🗝️ Recap & Key Terms 3 min

The CPU repeats fetch → decode → execute for every instruction. Fetch moves the address PC → MAR, brings the instruction into the MDR then the CIR, and adds 1 to the PC. Each instruction is an opcode plus an operand, taken from the CPU's limited instruction set.

Fetch–decode–execute cycle

The cycle in which instructions and data are fetched from memory, decoded and finally executed.

Program counter (PC)

A register that stores the address where the next instruction to be read can be found.

Current instruction register (CIR)

A register that stores the current instruction being decoded and executed.

Opcode

The part of a machine code instruction that identifies what action the CPU has to perform.

Operand

The part of a machine code instruction that identifies the data to be used (or where to find it).

Instruction set

The complete set of machine code instructions used by a particular CPU.

Homework 1 min

Task (≤ 15 min): Copy and complete, using register names and bus names: "The CPU copies the address in the ____ into the ____ using the ____ bus. The instruction is copied into the ____ using the ____ bus, then into the ____. The ____ is incremented. The instruction is decoded and then executed by sending signals along the ____ bus." [8]